#ifndef __LPDDR5_REGB_ARB_PORT1_H__
#define __LPDDR5_REGB_ARB_PORT1_H__

#include "main.h"

typedef struct __LPDDR5_REGB_ARB_PORT1 {
    volatile uint32_t RSVD_0;	 // offset: 0x0 Reserved 0.
	volatile uint32_t PCFGR;	 // offset: 0x4 default value: 0x501f read mask: 0xffffffff write mask 0x73ff
	volatile uint32_t PCFGW;	 // offset: 0x8 default value: 0x501f read mask: 0xffffffff write mask 0x73ff
    volatile uint32_t RSVD_0;	 // 0xc Reserved 0.
	volatile uint32_t RSVD_1;	 // 0x10 Reserved 1.
	volatile uint32_t RSVD_2;	 // 0x14 Reserved 2.
	volatile uint32_t RSVD_3;	 // 0x18 Reserved 3.
	volatile uint32_t RSVD_4;	 // 0x1c Reserved 4.
	volatile uint32_t RSVD_5;	 // 0x20 Reserved 5.
	volatile uint32_t RSVD_6;	 // 0x24 Reserved 6.
	volatile uint32_t RSVD_7;	 // 0x28 Reserved 7.
	volatile uint32_t RSVD_8;	 // 0x2c Reserved 8.
	volatile uint32_t RSVD_9;	 // 0x30 Reserved 9.
	volatile uint32_t RSVD_10;	 // 0x34 Reserved 10.
	volatile uint32_t RSVD_11;	 // 0x38 Reserved 11.
	volatile uint32_t RSVD_12;	 // 0x3c Reserved 12.
	volatile uint32_t RSVD_13;	 // 0x40 Reserved 13.
	volatile uint32_t RSVD_14;	 // 0x44 Reserved 14.
	volatile uint32_t RSVD_15;	 // 0x48 Reserved 15.
	volatile uint32_t RSVD_16;	 // 0x4c Reserved 16.
	volatile uint32_t RSVD_17;	 // 0x50 Reserved 17.
	volatile uint32_t RSVD_18;	 // 0x54 Reserved 18.
	volatile uint32_t RSVD_19;	 // 0x58 Reserved 19.
	volatile uint32_t RSVD_20;	 // 0x5c Reserved 20.
	volatile uint32_t RSVD_21;	 // 0x60 Reserved 21.
	volatile uint32_t RSVD_22;	 // 0x64 Reserved 22.
	volatile uint32_t RSVD_23;	 // 0x68 Reserved 23.
	volatile uint32_t RSVD_24;	 // 0x6c Reserved 24.
	volatile uint32_t RSVD_25;	 // 0x70 Reserved 25.
	volatile uint32_t RSVD_26;	 // 0x74 Reserved 26.
	volatile uint32_t RSVD_27;	 // 0x78 Reserved 27.
	volatile uint32_t RSVD_28;	 // 0x7c Reserved 28.
	volatile uint32_t RSVD_29;	 // 0x80 Reserved 29.
	volatile uint32_t RSVD_30;	 // 0x84 Reserved 30.
	volatile uint32_t RSVD_31;	 // 0x88 Reserved 31.
	volatile uint32_t RSVD_32;	 // 0x8c Reserved 32.
	volatile uint32_t PCTRL;	 // offset: 0x90 default value: 0x0 read mask: 0xffffffff write mask 0x1
	volatile uint32_t PCFGQOS0;	 // offset: 0x94 default value: 0x0 read mask: 0xffccfff0 write mask 0x33000f
	volatile uint32_t PCFGQOS1;	 // offset: 0x98 default value: 0x0 read mask: 0xf800f800 write mask 0x7ff07ff
	volatile uint32_t PCFGWQOS0;	 // offset: 0x9C default value: 0xe00 read mask: 0xfcccf0f0 write mask 0x3330f0f
	volatile uint32_t PCFGWQOS1;	 // offset: 0xA0 default value: 0x0 read mask: 0xf800f800 write mask 0x7ff07ff
} LPDDR5_REGB_ARB_PORT1_t;

/****************************** Bit definition for PCFGR register ********************************/

#define PCFGR_RD_PORT_PRIORITY_Pos		(0U)
#define PCFGR_RD_PORT_PRIORITY_Msk		(0x3ffUL << PCFGR_RD_PORT_PRIORITY_Pos)
#define PCFGR_RD_PORT_PRIORITY    		PCFGR_RD_PORT_PRIORITY_Msk


#define PCFGR_RD_PORT_AGING_EN_Pos		(12U)
#define PCFGR_RD_PORT_AGING_EN_Msk		(0x1UL << PCFGR_RD_PORT_AGING_EN_Pos)
#define PCFGR_RD_PORT_AGING_EN    		PCFGR_RD_PORT_AGING_EN_Msk


#define PCFGR_RD_PORT_URGENT_EN_Pos		(13U)
#define PCFGR_RD_PORT_URGENT_EN_Msk		(0x1UL << PCFGR_RD_PORT_URGENT_EN_Pos)
#define PCFGR_RD_PORT_URGENT_EN    		PCFGR_RD_PORT_URGENT_EN_Msk


#define PCFGR_RD_PORT_PAGEMATCH_EN_Pos		(14U)
#define PCFGR_RD_PORT_PAGEMATCH_EN_Msk		(0x1UL << PCFGR_RD_PORT_PAGEMATCH_EN_Pos)
#define PCFGR_RD_PORT_PAGEMATCH_EN    		PCFGR_RD_PORT_PAGEMATCH_EN_Msk


/****************************** Bit definition for PCFGW register ********************************/

#define PCFGW_WR_PORT_PRIORITY_Pos		(0U)
#define PCFGW_WR_PORT_PRIORITY_Msk		(0x3ffUL << PCFGW_WR_PORT_PRIORITY_Pos)
#define PCFGW_WR_PORT_PRIORITY    		PCFGW_WR_PORT_PRIORITY_Msk


#define PCFGW_WR_PORT_AGING_EN_Pos		(12U)
#define PCFGW_WR_PORT_AGING_EN_Msk		(0x1UL << PCFGW_WR_PORT_AGING_EN_Pos)
#define PCFGW_WR_PORT_AGING_EN    		PCFGW_WR_PORT_AGING_EN_Msk


#define PCFGW_WR_PORT_URGENT_EN_Pos		(13U)
#define PCFGW_WR_PORT_URGENT_EN_Msk		(0x1UL << PCFGW_WR_PORT_URGENT_EN_Pos)
#define PCFGW_WR_PORT_URGENT_EN    		PCFGW_WR_PORT_URGENT_EN_Msk


#define PCFGW_WR_PORT_PAGEMATCH_EN_Pos		(14U)
#define PCFGW_WR_PORT_PAGEMATCH_EN_Msk		(0x1UL << PCFGW_WR_PORT_PAGEMATCH_EN_Pos)
#define PCFGW_WR_PORT_PAGEMATCH_EN    		PCFGW_WR_PORT_PAGEMATCH_EN_Msk


/****************************** Bit definition for PCTRL register ********************************/

#define PCTRL_PORT_EN_Pos		(0U)
#define PCTRL_PORT_EN_Msk		(0x1UL << PCTRL_PORT_EN_Pos)
#define PCTRL_PORT_EN    		PCTRL_PORT_EN_Msk


/****************************** Bit definition for PCFGQOS0 register ********************************/

#define PCFGQOS0_RQOS_MAP_LEVEL1_Pos		(0U)
#define PCFGQOS0_RQOS_MAP_LEVEL1_Msk		(0xfUL << PCFGQOS0_RQOS_MAP_LEVEL1_Pos)
#define PCFGQOS0_RQOS_MAP_LEVEL1    		PCFGQOS0_RQOS_MAP_LEVEL1_Msk


#define PCFGQOS0_RQOS_MAP_REGION0_Pos		(16U)
#define PCFGQOS0_RQOS_MAP_REGION0_Msk		(0x3UL << PCFGQOS0_RQOS_MAP_REGION0_Pos)
#define PCFGQOS0_RQOS_MAP_REGION0    		PCFGQOS0_RQOS_MAP_REGION0_Msk


#define PCFGQOS0_RQOS_MAP_REGION1_Pos		(20U)
#define PCFGQOS0_RQOS_MAP_REGION1_Msk		(0x3UL << PCFGQOS0_RQOS_MAP_REGION1_Pos)
#define PCFGQOS0_RQOS_MAP_REGION1    		PCFGQOS0_RQOS_MAP_REGION1_Msk


/****************************** Bit definition for PCFGQOS1 register ********************************/

#define PCFGQOS1_RQOS_MAP_TIMEOUTB_Pos		(0U)
#define PCFGQOS1_RQOS_MAP_TIMEOUTB_Msk		(0x7ffUL << PCFGQOS1_RQOS_MAP_TIMEOUTB_Pos)
#define PCFGQOS1_RQOS_MAP_TIMEOUTB    		PCFGQOS1_RQOS_MAP_TIMEOUTB_Msk


#define PCFGQOS1_RQOS_MAP_TIMEOUTR_Pos		(16U)
#define PCFGQOS1_RQOS_MAP_TIMEOUTR_Msk		(0x7ffUL << PCFGQOS1_RQOS_MAP_TIMEOUTR_Pos)
#define PCFGQOS1_RQOS_MAP_TIMEOUTR    		PCFGQOS1_RQOS_MAP_TIMEOUTR_Msk


/****************************** Bit definition for PCFGWQOS0 register ********************************/

#define PCFGWQOS0_WQOS_MAP_LEVEL1_Pos		(0U)
#define PCFGWQOS0_WQOS_MAP_LEVEL1_Msk		(0xfUL << PCFGWQOS0_WQOS_MAP_LEVEL1_Pos)
#define PCFGWQOS0_WQOS_MAP_LEVEL1    		PCFGWQOS0_WQOS_MAP_LEVEL1_Msk


#define PCFGWQOS0_WQOS_MAP_LEVEL2_Pos		(8U)
#define PCFGWQOS0_WQOS_MAP_LEVEL2_Msk		(0xfUL << PCFGWQOS0_WQOS_MAP_LEVEL2_Pos)
#define PCFGWQOS0_WQOS_MAP_LEVEL2    		PCFGWQOS0_WQOS_MAP_LEVEL2_Msk


#define PCFGWQOS0_WQOS_MAP_REGION0_Pos		(16U)
#define PCFGWQOS0_WQOS_MAP_REGION0_Msk		(0x3UL << PCFGWQOS0_WQOS_MAP_REGION0_Pos)
#define PCFGWQOS0_WQOS_MAP_REGION0    		PCFGWQOS0_WQOS_MAP_REGION0_Msk


#define PCFGWQOS0_WQOS_MAP_REGION1_Pos		(20U)
#define PCFGWQOS0_WQOS_MAP_REGION1_Msk		(0x3UL << PCFGWQOS0_WQOS_MAP_REGION1_Pos)
#define PCFGWQOS0_WQOS_MAP_REGION1    		PCFGWQOS0_WQOS_MAP_REGION1_Msk


#define PCFGWQOS0_WQOS_MAP_REGION2_Pos		(24U)
#define PCFGWQOS0_WQOS_MAP_REGION2_Msk		(0x3UL << PCFGWQOS0_WQOS_MAP_REGION2_Pos)
#define PCFGWQOS0_WQOS_MAP_REGION2    		PCFGWQOS0_WQOS_MAP_REGION2_Msk


/****************************** Bit definition for PCFGWQOS1 register ********************************/

#define PCFGWQOS1_WQOS_MAP_TIMEOUT1_Pos		(0U)
#define PCFGWQOS1_WQOS_MAP_TIMEOUT1_Msk		(0x7ffUL << PCFGWQOS1_WQOS_MAP_TIMEOUT1_Pos)
#define PCFGWQOS1_WQOS_MAP_TIMEOUT1    		PCFGWQOS1_WQOS_MAP_TIMEOUT1_Msk


#define PCFGWQOS1_WQOS_MAP_TIMEOUT2_Pos		(16U)
#define PCFGWQOS1_WQOS_MAP_TIMEOUT2_Msk		(0x7ffUL << PCFGWQOS1_WQOS_MAP_TIMEOUT2_Pos)
#define PCFGWQOS1_WQOS_MAP_TIMEOUT2    		PCFGWQOS1_WQOS_MAP_TIMEOUT2_Msk


/****************************** Inline function for PCFGR register ********************************/

static inline void set_pcfgr_rd_port_priority(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGR, PCFGR_RD_PORT_PRIORITY, VAL << PCFGR_RD_PORT_PRIORITY_Pos);
}

static inline uint32_t get_pcfgr_rd_port_priority(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGR, PCFGR_RD_PORT_PRIORITY) >> PCFGR_RD_PORT_PRIORITY_Pos);
}

static inline void set_pcfgr_rd_port_aging_en(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGR, PCFGR_RD_PORT_AGING_EN, VAL << PCFGR_RD_PORT_AGING_EN_Pos);
}

static inline uint32_t get_pcfgr_rd_port_aging_en(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGR, PCFGR_RD_PORT_AGING_EN) >> PCFGR_RD_PORT_AGING_EN_Pos);
}

static inline void set_pcfgr_rd_port_urgent_en(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGR, PCFGR_RD_PORT_URGENT_EN, VAL << PCFGR_RD_PORT_URGENT_EN_Pos);
}

static inline uint32_t get_pcfgr_rd_port_urgent_en(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGR, PCFGR_RD_PORT_URGENT_EN) >> PCFGR_RD_PORT_URGENT_EN_Pos);
}

static inline void set_pcfgr_rd_port_pagematch_en(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGR, PCFGR_RD_PORT_PAGEMATCH_EN, VAL << PCFGR_RD_PORT_PAGEMATCH_EN_Pos);
}

static inline uint32_t get_pcfgr_rd_port_pagematch_en(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGR, PCFGR_RD_PORT_PAGEMATCH_EN) >> PCFGR_RD_PORT_PAGEMATCH_EN_Pos);
}

/****************************** Inline function for PCFGW register ********************************/

static inline void set_pcfgw_wr_port_priority(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGW, PCFGW_WR_PORT_PRIORITY, VAL << PCFGW_WR_PORT_PRIORITY_Pos);
}

static inline uint32_t get_pcfgw_wr_port_priority(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGW, PCFGW_WR_PORT_PRIORITY) >> PCFGW_WR_PORT_PRIORITY_Pos);
}

static inline void set_pcfgw_wr_port_aging_en(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGW, PCFGW_WR_PORT_AGING_EN, VAL << PCFGW_WR_PORT_AGING_EN_Pos);
}

static inline uint32_t get_pcfgw_wr_port_aging_en(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGW, PCFGW_WR_PORT_AGING_EN) >> PCFGW_WR_PORT_AGING_EN_Pos);
}

static inline void set_pcfgw_wr_port_urgent_en(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGW, PCFGW_WR_PORT_URGENT_EN, VAL << PCFGW_WR_PORT_URGENT_EN_Pos);
}

static inline uint32_t get_pcfgw_wr_port_urgent_en(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGW, PCFGW_WR_PORT_URGENT_EN) >> PCFGW_WR_PORT_URGENT_EN_Pos);
}

static inline void set_pcfgw_wr_port_pagematch_en(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGW, PCFGW_WR_PORT_PAGEMATCH_EN, VAL << PCFGW_WR_PORT_PAGEMATCH_EN_Pos);
}

static inline uint32_t get_pcfgw_wr_port_pagematch_en(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGW, PCFGW_WR_PORT_PAGEMATCH_EN) >> PCFGW_WR_PORT_PAGEMATCH_EN_Pos);
}

/****************************** Inline function for PCTRL register ********************************/

static inline void set_pctrl_port_en(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCTRL, PCTRL_PORT_EN, VAL << PCTRL_PORT_EN_Pos);
}

static inline uint32_t get_pctrl_port_en(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCTRL, PCTRL_PORT_EN) >> PCTRL_PORT_EN_Pos);
}

/****************************** Inline function for PCFGQOS0 register ********************************/

static inline void set_pcfgqos0_rqos_map_level1(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGQOS0, PCFGQOS0_RQOS_MAP_LEVEL1, VAL << PCFGQOS0_RQOS_MAP_LEVEL1_Pos);
}

static inline uint32_t get_pcfgqos0_rqos_map_level1(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGQOS0, PCFGQOS0_RQOS_MAP_LEVEL1) >> PCFGQOS0_RQOS_MAP_LEVEL1_Pos);
}

static inline void set_pcfgqos0_rqos_map_region0(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGQOS0, PCFGQOS0_RQOS_MAP_REGION0, VAL << PCFGQOS0_RQOS_MAP_REGION0_Pos);
}

static inline uint32_t get_pcfgqos0_rqos_map_region0(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGQOS0, PCFGQOS0_RQOS_MAP_REGION0) >> PCFGQOS0_RQOS_MAP_REGION0_Pos);
}

static inline void set_pcfgqos0_rqos_map_region1(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGQOS0, PCFGQOS0_RQOS_MAP_REGION1, VAL << PCFGQOS0_RQOS_MAP_REGION1_Pos);
}

static inline uint32_t get_pcfgqos0_rqos_map_region1(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGQOS0, PCFGQOS0_RQOS_MAP_REGION1) >> PCFGQOS0_RQOS_MAP_REGION1_Pos);
}

/****************************** Inline function for PCFGQOS1 register ********************************/

static inline void set_pcfgqos1_rqos_map_timeoutb(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGQOS1, PCFGQOS1_RQOS_MAP_TIMEOUTB, VAL << PCFGQOS1_RQOS_MAP_TIMEOUTB_Pos);
}

static inline uint32_t get_pcfgqos1_rqos_map_timeoutb(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGQOS1, PCFGQOS1_RQOS_MAP_TIMEOUTB) >> PCFGQOS1_RQOS_MAP_TIMEOUTB_Pos);
}

static inline void set_pcfgqos1_rqos_map_timeoutr(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGQOS1, PCFGQOS1_RQOS_MAP_TIMEOUTR, VAL << PCFGQOS1_RQOS_MAP_TIMEOUTR_Pos);
}

static inline uint32_t get_pcfgqos1_rqos_map_timeoutr(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGQOS1, PCFGQOS1_RQOS_MAP_TIMEOUTR) >> PCFGQOS1_RQOS_MAP_TIMEOUTR_Pos);
}

/****************************** Inline function for PCFGWQOS0 register ********************************/

static inline void set_pcfgwqos0_wqos_map_level1(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGWQOS0, PCFGWQOS0_WQOS_MAP_LEVEL1, VAL << PCFGWQOS0_WQOS_MAP_LEVEL1_Pos);
}

static inline uint32_t get_pcfgwqos0_wqos_map_level1(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGWQOS0, PCFGWQOS0_WQOS_MAP_LEVEL1) >> PCFGWQOS0_WQOS_MAP_LEVEL1_Pos);
}

static inline void set_pcfgwqos0_wqos_map_level2(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGWQOS0, PCFGWQOS0_WQOS_MAP_LEVEL2, VAL << PCFGWQOS0_WQOS_MAP_LEVEL2_Pos);
}

static inline uint32_t get_pcfgwqos0_wqos_map_level2(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGWQOS0, PCFGWQOS0_WQOS_MAP_LEVEL2) >> PCFGWQOS0_WQOS_MAP_LEVEL2_Pos);
}

static inline void set_pcfgwqos0_wqos_map_region0(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGWQOS0, PCFGWQOS0_WQOS_MAP_REGION0, VAL << PCFGWQOS0_WQOS_MAP_REGION0_Pos);
}

static inline uint32_t get_pcfgwqos0_wqos_map_region0(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGWQOS0, PCFGWQOS0_WQOS_MAP_REGION0) >> PCFGWQOS0_WQOS_MAP_REGION0_Pos);
}

static inline void set_pcfgwqos0_wqos_map_region1(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGWQOS0, PCFGWQOS0_WQOS_MAP_REGION1, VAL << PCFGWQOS0_WQOS_MAP_REGION1_Pos);
}

static inline uint32_t get_pcfgwqos0_wqos_map_region1(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGWQOS0, PCFGWQOS0_WQOS_MAP_REGION1) >> PCFGWQOS0_WQOS_MAP_REGION1_Pos);
}

static inline void set_pcfgwqos0_wqos_map_region2(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGWQOS0, PCFGWQOS0_WQOS_MAP_REGION2, VAL << PCFGWQOS0_WQOS_MAP_REGION2_Pos);
}

static inline uint32_t get_pcfgwqos0_wqos_map_region2(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGWQOS0, PCFGWQOS0_WQOS_MAP_REGION2) >> PCFGWQOS0_WQOS_MAP_REGION2_Pos);
}

/****************************** Inline function for PCFGWQOS1 register ********************************/

static inline void set_pcfgwqos1_wqos_map_timeout1(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGWQOS1, PCFGWQOS1_WQOS_MAP_TIMEOUT1, VAL << PCFGWQOS1_WQOS_MAP_TIMEOUT1_Pos);
}

static inline uint32_t get_pcfgwqos1_wqos_map_timeout1(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGWQOS1, PCFGWQOS1_WQOS_MAP_TIMEOUT1) >> PCFGWQOS1_WQOS_MAP_TIMEOUT1_Pos);
}

static inline void set_pcfgwqos1_wqos_map_timeout2(LPDDR5_REGB_ARB_PORT1_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->PCFGWQOS1, PCFGWQOS1_WQOS_MAP_TIMEOUT2, VAL << PCFGWQOS1_WQOS_MAP_TIMEOUT2_Pos);
}

static inline uint32_t get_pcfgwqos1_wqos_map_timeout2(LPDDR5_REGB_ARB_PORT1_t *INST)
{
	return (uint32_t)(READ_BIT(INST->PCFGWQOS1, PCFGWQOS1_WQOS_MAP_TIMEOUT2) >> PCFGWQOS1_WQOS_MAP_TIMEOUT2_Pos);
}

#endif // __LPDDR5_REGB_ARB_PORT1_H__
